Semiconductor device fabrication involves many stages of fabrication, including a front end stage of fabrication and a back end stage of fabrication. The front end stage of fabrication may further include various processes such as deposition, lithography and etching/patterning, wafer acceptance testing and chip probe testing. The back end stage of fabrication follows the front end stage and may include other additional processes such as wafer dicing, chip bonding, chip packaging, and final testing.
Of the front end stage of fabrication processes, the chip probe testing is subsequently performed for the electrical performance, which is usually done at a chip level. For a wafer having a plurality of light emitting devices (LEDs), it is usually bonded to other substrate in a three dimensional (3D) packaging. The optical test for LEDs can only be done after the 3D packaging and sawing at the back end stage of fabrication. However, if a LED fails the optical test, the LED chip, along with other components in the 3D package, is discarded, which increases the fabrication cost since other components in the 3D package have to be scraped as well. Therefore, an apparatus and method to effectively test LED devices for both optical and electrical performances at chip level are needed to address the issues identified above.